An integrated circuit contains vias formed using a dual damascene process. Some of the vias are formed in interconnect lines which are significantly wider than minimum width interconnect lines at the same level. Dual damascene vias in wide interconnect lines have flared profiles in which the tops of the vias are significantly wider than the bottoms of the vias. Flaring leads to more liner metal in the bottom of the vias, disadvantageously causing higher and/or erratic via resistance.